By way of example, the second memory is a memory for storing data which actually need to be stored in the first memory but cannot be stored there because the first memory's storage elements which are to be used for storing these data are faulty. Memories like the second memory are frequently also referred to as redundancy memories. In an arrangement of this type, the switching devices can stipulate whether access to the first memory involves output of the data stored in the first memory or the data stored in the second memory.
A conventional arrangement of this type is illustrated in FIG. 4.
The arrangement shown in FIG. 4 comprises a first memory 401, a first address decoder 402, a second address decoder 403, a sense-amplifier and selection unit 404, a second memory 405, a sense-amplifier unit 406, a control device 407 and a checking device 408.
The main component of the arrangement shown in FIG. 4 is the first memory 401. This memory is a memory for storing data, and this memory is accessed as standard when data are to be written to the arrangement or when data are to be read from the arrangement. The first memory 401 may contain errors, like any electrical or electronic device. More precisely, it may contain faulty storage elements in which no data can or should be stored. The data which cannot or should not be stored in the first memory 401 on account of faults in the first memory 401 are stored in the second memory 405. The second memory 405 is a redundancy memory for storing data which actually need to be stored in the first memory 401 but cannot be stored there because the first memory's storage elements which are to be used for the storage are faulty.
The control device 407, the checking device 408 and portions of the sense-amplifier and selection unit 404 ensure that instances of access to faulty areas of the first memory 401 involve output of data stored in the second memory 405.
This is explained in more detail below:
If data are to be read from the memory 401, the arrangement is supplied with an address A at which the required data are stored within the first memory 401. The address A is supplied to the first address decoder 402 and to the second address decoder 403. The first address decoder 402 selects the word line to which the storage elements which are to be read are connected, and the second address decoder 403 selects the bit lines to which the storage elements which are to be read are connected. The bit lines selected by the second address decoder 403 are connected to the sense-amplifier and selection unit 404 via lines 450. The sense-amplifier and selection unit 404 contains a number of sense amplifiers 409 which corresponds to the number of lines 450, and the same number of switching devices, formed generally by multiplexers 410. The input sides of the sense amplifiers are connected to the lines 450, and the sense amplifiers use known methods to ascertain the content of the storage elements which are to be read in the first memory 401.
At the same time as data are being read from the first memory 401, data are read from the second memory 405. In the example under consideration, all storage elements which are connected to a word line in the second memory 405 which (word line) is associated with the selected word line in the first memory 401 are respectively read. In the example under consideration, three respective storage elements in the second memory are read. The bit lines 451 connected to the storage elements in the second memory 405 which are to be read are connected to the sense-amplifier unit 406. The sense-amplifier unit 406 contains a number of sense amplifiers which corresponds to the number of lines 451. The input sides of the sense amplifiers are connected to the lines 451, and the sense amplifiers use known methods to ascertain the content of the storage elements which are to be read in the second memory 405.
The output signals from the sense amplifiers 409 in the sense-amplifier and selection unit 404 and the output signals from the sense amplifiers in the sense-amplifier unit 406 are supplied to the multiplexers 410 provided in the sense-amplifier and selection unit 404. More precisely, each multiplexer 410 is supplied with the output signal from an associated sense amplifier 409 in the sense-amplifier and selection unit 404, and with the output signals from all of the sense amplifiers in the sense-amplifier unit 406. The multiplexers 410 are controlled by the control device 407. The multiplexers 410 output data DOUT which are simultaneously the data which are to be output by the arrangement as a reaction to the access to the arrangement.
The multiplexers 410 are controlled by the control device 407 on the basis of whether or not the storage elements which are to be read in the first memory 401 include faulty storage elements.
Whether this is the case is communicated to the control device 407 by the checking device 408. The checking device 408 stores the addresses whose use involves access to faulty storage elements. The checking device 408 checks whether the address A supplied to the arrangement matches one of the addresses stored in the checking device 408, and communicates the result of this check to the control device 407.
The control device 407 therefore ascertains how it needs to actuate the multiplexers 410. It actuates the multiplexers 410 such                that they switch through the signal which the sense amplifier 409 supplies to them if the storage element in the first memory 401 whose content is represented by the signal in question is not faulty, and        that they switch through one of the signals which the sense-amplifier unit 406 supplies to them if the storage element in the first memory 401 whose content is represented by the output signal from the sense amplifier is faulty.        
In this manner, even if the first memory 401 contains faulty storage elements, it is always possible to output correct data, specifically without the need for the user to consider any special features for this purpose; from the point of view of the user, it makes no difference whether a sound first memory or an unsound first memory is being accessed.
However, replacing faulty storage elements in the first memory 401 with associated memory elements in the second memory 405 is associated with significant complexity. Particularly the comparisons between the address A and the addresses stored in the checking device 408 and also the ascertainment, performed by the control device 407, of the control signals controlling the multiplexers 410 are very time-consuming, which means that the data DOUT which are output from arrangements of the type shown in FIG. 4 are generally available at a later time than is the case with arrangements without redundancy memories.